The present invention relates to personal computer systems and more particularly to personal computer systems having multiple bus architectures.
Computer systems typically include more than one bus, each bus in the system having devices attached thereto which communicate locally with each other over the bus. Examples of the different types of buses present in typical computer systems are a local bus, to which the host central processing unit (CPU) is directly coupled, a system bus to which the host central processing unit is also coupled, and one or more peripheral (or I/O) buses. System-wide communication over different buses is required, To permit system-wide communication between devices on different buses, bus-to-bus bridges (interfaces) are provided to match the communications protocol of one bus with that of another.
Each bus-to-bus bridge in a multi-bus computer system is used to connect two buses in the system. Various types of buses are available to construct a given computer system. One such bus which is becoming widely accepted is the PCI (Peripheral Component Interconnect) bus, which is capable of performing significant data transfer in a relatively short period of time (up to 120 megabytes of data per second). The PCI bus achieves this high level of performance, in part, because it may be directly linked to other high speed buses, such as system buses to which a CPU may be connected, and thus may provide for rapid transfer of data between devices attached to the PCI bus and devices attached to the system bus. In fact, the operation of several high integration devices, such as certain graphics package controllers, require a direct link to a system bus through a high performance bus such as the PCI bus. In addition, the PCI bus architecture does not require any "glue logic" to operate peripheral devices connected to it. Glue logic for other buses typically consists of miscellaneous hardware components such as decoders, buffers or latches that are installed intermediate the peripheral devices and the bus.
The primary PCI bus operates on a synchronous clock signal of 33 MHz, and the strings of data transmitted over the PCI bus are 32 bits long. A 32-bit data string on the PCI bus is called a double word (DWORD), which is divided into 4 bytes each comprising 8 bits of data. The address and data information carried by the PCI bus are multiplexed onto one signal. Multiplexing eliminates the need for separate address and data lines, which in turn, reduces the amount of signals required in a PCI bus environment as opposed to other bus architectures. The number of signals required in PCI bus architecture is between 45-47 while non-multiplexed buses typically require twice this number. Accordingly, because the number of signals are reduced, the number of connection pins required to support a device linked to the PCI bus is also reduced by a corresponding number. PCI architecture is thus particularly adapted for highly integrated desktop computer systems.
A more detailed description of the structure and operation of PCI bus architecture is provided in "Peripheral Component Interconnect (PCI) Revision 2.0 Specification", published Apr. 30, 1993; "Preliminary PCI System Design Guide", revision 0.6, published Nov. 1, 1992, and "Peripheral Component Interconnect (PCI) Add-in Board/Connector Addendum", (Draft) published 6 Nov. 1992; all by the PCI Special Interest Group, the contents of which references are incorporated herein by reference as if they were fully set forth.
One example of an I/O bus that can be coupled to a PCI bus is the Micro Channel bus. Micro Channel buses can be coupled to the PCI bus via a bridge controller. The purpose of the bridge controller is to transform PCI signals and protocol to Micro Channel signals and protocol and vise versa. In addition, the bridge controller must determine which addresses (both I/O and memory) are in use by devices on its bus. The PCI specification provides two methods for recognizing addresses: (1) subtractive decode and (2) positive decode. The subtractive decode method requires minimum hardware circuitry, however, it introduces delays while the bridge waits to determine if another device responds to the address. Also, only one bridge on a bus may use subtractive decode. The positive decode method uses address registers inside the bridge controller to determine which address to claim and pass on to the devices coupled to the bridge's secondary bus. For PCI to Micro Channel bridges, the number of address range registers required depends on the number of slots on the Micro Channel, the types of devices and the number of devices on the bus. Another factor that may affect the number of registers is the number of other Micro Channel buses attached to the same PCI bus.
Developments in the personal computer industry, such as the PCI bus, cause operating system and other software to be changed to or extended to effectively use the hardware. As the hardware evolves over time, the impacts to software continue. Therefore, there is a need for a computer system to avoid or minimize the software impacts as the hardware evolves.